During the manufacture of semiconductor memory devices, it is necessary to test each memory to ensure it is operating properly. Electronic and computer systems containing semiconductor memories also normally test the memories when power is initially applied to the system. A typical memory device includes a number of arrays, each array including a number of memory cells arranged in rows and columns. During testing of the memory devices, each memory cell must be tested to ensure it is operating properly. In a typical prior art test method, data having a first binary value (e.g., a “1”) is written to and read from all memory cells in the arrays, and thereafter data having a different binary value (e.g., a “0”) is typically written to and read from the memory cells. A memory cell is determined to be defective when the data written to the memory cell does not equal that read from the memory cell. As understood by one skilled in the art, other test data patterns may be utilized in testing the memory cells, such as an alternating bit pattern “101010 . . . 0” written to the memory cells in each row of the arrays.
In a typical test configuration, an automated memory tester is coupled to address, data, and control buses of the memory device, and applies signals to these buses to perform the desired tests. As the storage capacity of memory devices increase, the number of memory cells and hence the number of data transfer operations the tester must perform correspondingly increases. For example, in a memory array having n rows and m columns of memory cells, the tester performs n*m cell accesses in writing the first binary data values to all the memory cells in the array, and thereafter performs n*m cell accesses in reading the same data. The tester must once again perform n*m accesses in writing data having a second binary value to each memory cell, and the same number of accesses in reading this data. The tester thus performs a total of four times n*m cell accesses, each of which requires a bus cycle to perform.
Data compression has been used by some testers to reduce the number of bus cycles required to test memory cells. Data compression generally relies on some means of quickly writing data to the memory cells of the memory device, and then reducing the amount of data that must be read from the memory device to indicate a pass or a fail condition. For example, sense amplifiers of an SDRAM device may be held at a particular logic level, such as a level corresponding to a binary “1” value, and the rows of memory cells sequentially activated, thereby quickly writing a binary value of “1” to each of the memory cells in the array. When data is read from the memory device, the binary values from all of the memory cells or groups of memory cells can be applied to an AND gate or other logic circuit. The logic circuit outputs a logic “1” if all of the memory cells in the row properly functioned to store the correct binary value. A similar process can then be used to write a binary value of “0” to all of the memory cells and then read the values stored in the memory cells. The results of reading each row can then be combined by conventional means so that the memory device will output a single binary value indicating either a pass or a fail condition.
Although compressed data testing of memory devices as described above can quickly provide a tester with an indication of whether or not all memory cells are functioning properly, it does not allow the tester to determine if multiple memory cells are malfunctioning or to identify the locations of one or more memory cell failures. Yet knowing the number and location of memory cell failures can provide valuable information during production testing since such information can be used to correct processing deficiencies. To provide complete testing information, the tester must read data from every memory cell in the memory device. The data read from each memory cell are then compared to the data written to that same memory cells, and any discrepancy is recorded as an error for that cell. The error data are then stored in a high-speed memory, known as an Error Catch RAM (“ECR”). Once the data from the memory device have been captured by the ECR, an error map identifying the failed memory cells is created.
Two approaches have conventionally been used to implement an ECR. One approach is to use an expensive high-speed static random access memory (“SRAM”) device, which is capable of capturing the read data from the memory device at the required operating speed. The other approach is to use interleaved banks of DRAM to capture the read data. Interleaving pages of DRAM can be less expensive than using a high-speed SDRAM device, but poses additional complications in reconstructing the read data. The difficulty in using either of these approaches is exacerbated by memory devices having significantly greater storage capacities, such as state-of-the-art NAND Flash memory devices. As a result, conventional testers must separately test different portions of such high-capacity memory devices, which requires a significant amount of time to complete a test.
There is therefore a need for a compression system and the method that can be used by memory testers to provide an error map of the memory device being tested that can function at the normal operating speed of memory devices and that does not require a very large data storage device.